As semiconductor memory devices become highly integrated, design rules may be reduced to integrate many elements per unit area. If design rules are reduced, lengths and areas of elements may decrease. Therefore, a current driving ability of an element may be lowered, and passive switching characteristics of the element may deteriorate due to short-channel effects. A vertical channel transistor may be capable of reducing leakage current caused by drain induced barrier lowering (DIBL), punch through and the like while providing relatively high current driving ability.
To reduce process margin limits due to narrow distances between word lines and to increase integration, a highly integrated semiconductor memory device having vertical channel transistors may use a structure in which a buried diffusion bit line is formed on a body, and a vertical gate electrode is then formed on the buried diffusion bit line. However, the buried diffusion bit line may have relatively high resistance. Accordingly, a data transfer speed and access time of the semiconductor memory device may increase, and application of buried diffusion bit lines to memory devices such as high-speed DRAMs may be difficult.